1. Technical Field
The present invention relates to a wafer level package having a cylindrical capacitor and a method of fabricating the same.
2. Description of the Related Art
Recently, the electronics industry has advanced so that products which are lightweight, slim, short and small and which have multi-functionality and high performance are supplied at low price. To this end, a packaging technique is employed. In particular, a wafer level package which is packaged on a wafer is receiving attention these days.
Typically, a wafer level package includes a capacitor embedded therein in order to achieve signal stability. FIG. 1 is a cross-sectional view showing a wafer level package including a capacitor having a two-dimensional planar structure according to a conventional technique.
As shown in FIG. 1, the wafer level package 10 including a capacitor having a two-dimensional planar structure according to the conventional technique includes a wafer chip 12 having a bonding pad provided at the upper surface thereof and an insulating layer 18 formed thereon and exposing the bonding pad, a lower electrode 34 formed on the insulating layer 18, a dielectric layer 38 formed on the lower electrode 34, a redistribution layer 36 one side of which is connected to the bonding pad and which extends onto the dielectric layer 38 along the upper surface of the insulating layer 18 from the bonding pad, a passivation layer 28 formed on the insulating layer 18 to cover the redistribution layer 36, a metal post 30 formed on the other side of the redistribution layer 36, and a solder ball 14 formed on the metal post 30.
As such, the redistribution layer 36 extending onto the dielectric layer 38 may simultaneously function as an upper electrode of a capacitor unit 32. Specifically, the capacitor unit 32 has a two-dimensional planar structure composed of the lower electrode 34, the redistribution layer 36 and the dielectric layer 38.
However, because the capacitor unit 32 provided in the wafer level package 10 has the two-dimensional planar structure described above, electrostatic capacity may be increased only by using a dielectric layer 38 having a higher dielectric constant, enlarging the area of the lower electrode 34 and the upper electrode, or reducing the distance between the electrodes. Hence, limitations are imposed on increasing the electrostatic capacity.
Also, the capacitor unit 32 having such a two-dimensional planar structure should be manufactured through an additional process (e.g. sputtering and patterning), undesirably increasing the manufacturing cost. Furthermore, as the thickness of the capacitor unit 32 is increased, problems related to material waste and an increase in the process time required to manufacture the wafer level package 10 may occur.